1. Field of the Invention
The present invention relates to a voltage controlled oscillator (VCO) and a PLL (phase locked loop) circuit.
2. Description of the Related Art
A clock synchronized type semiconductor device generally has a PLL circuit for generating an internal clock (a clock used in an internal circuit) synchronized with an external clock supplied via an external terminal. The PLL circuit has a voltage controlled oscillator generating the internal clock, and in order to synchronize the internal clock with the external clock, it compares the phase of the external clock and that of the internal clock and regulates a control voltage of the voltage controlled oscillator according to a result of the phase comparison.
For a lock range of the PLL circuit (a frequency range of clocks generated by the PLL circuit), the wider, the better. However, the lock range of the PLL circuit is narrowed due to a reduction in the range of the control voltage owing to a decrease in power supply voltage, or due to a decrease in oscillation frequency of the voltage controlled oscillator owing to fluctuation in power supply voltage, variation in fabricated semiconductor elements, or fluctuation in operating temperature. In view of solving the above-identified problem, for example, Japanese Unexamined Patent Application Publication No. Hei 9-284130 discloses a PLL circuit that includes a plurality of voltage controlled oscillators whose oscillation frequency bands differ from one another and outputs as an internal clock one of clocks generated by the voltage controlled oscillators according to the frequency of an external clock. Further, Japanese Unexamined Patent Application Publication No. Hei 8-180676 discloses a PLL circuit that includes a ring oscillator having a plurality of inverters and changes the number of inverters to be loop-connected for generating an internal clock in the ring oscillator, based on information relating to the operating frequency of a semiconductor memory (operating frequency related information).